This invention relates to a failure recovery arrangement for use in a data processing system.
A data processing system of the type described, comprises a system bus, a local bus, and at least one peripheral control processor. The peripheral control processor is operable in a normal state of operation and is put into a down state when a failure occurs during progress of the normal state.
A conventional failure recovery informing arrangement comprises a failure occurrence signal producing circuit. Connected to the peripheral control processor and to a first signal transmission line, the failure occurrence signal producing circuit detects the downstate of the peripheral control processor and produces a failure occurrence signal, indicative of occurrence of the failure, and delivers the failure occurrence signal to the first signal transmission line.
An input-output processor is connected to the first signal transmission line. Responsive to the failure occurrence signal, the input-output processor produces a recovery command signal and delivers the recovery command signal to the peripheral control processor through a second signal transmission line connected between the input-output processor and the peripheral control processor. The recovery command signal comprises an initializing signal and an informing signal.
Supplied to the peripheral control processor through the second signal transmission line, the initializing signal is for turning the down state back to the normal state. The peripheral control processor has to obtain the informing signal which informs that the down state is turned back to the normal state after occurrence of the failure. This is because the peripheral control processor supplies the input-output processor with a completion signal representative of complete recovery of the failure after the peripheral control processor is turned back to the normal state. The reason will become clear later in the description why the peripheral control processor must deliver the completion signal to the input-output processor.
Although the input-output processor is connected to the peripheral control processor through the above-mentioned local bus, it is impossible to use the local bus in supplying the recovery command signal from the input-output processor to the peripheral control processor before the peripheral control processor is turned back to the normal state. Provision of the second signal transmission line renders hardware of the failure recovery informing arrangement complicated.